Field of the Invention
This invention relates to computing systems, and more particularly, to efficiently floor planning a memory.
Background
Generally speaking, a semiconductor chip includes at least one processing unit coupled to a memory. The processing unit processes instructions of a predetermined algorithm. The processing may include fetching instructions and data, decoding instructions, executing instructions and storing results. While executing instructions, the processing unit may perform calculations and generate memory access requests. The memory may be accessed for the fetching operations and the generated memory access requests, which include storing results.
In some embodiments, the processing unit and the memory are on a same die. In other embodiments, the processing unit and the memory are on different dies within a same package such as a system-on-a-chip (SOC). The die or the package may include other units or components, such as an interface unit, in addition to the processing unit and the memory. The dimensions of the individual components have limits in order to place all of the components on a same die or a same package. For several types of memory, the dimensions may exceed limits for efficient placement.
In some embodiments, the dimensions of the memory, such as the height or the width, may be large enough that they interfere with the placement of other components. In some cases the other components may not even fit within the same die or the same package. Consequently, the chip may be rendered inoperable without significant redesign. In other cases the components may fit within the same die or package, but their placement may be such that unused space on the die or package results. In this case, the placement of the components may be deemed inefficient, as otherwise usable space is rendered unusable due to the placement. In addition to the above, altering the dimensions of the memory may be difficult as the row or entry decoding is typically dependent on a 2x value. This value may sets one dimension, such as the width, while the dimensions of an individual memory cell may set the height. In addition, dimensions may be determined by the bit separation or interleaving used to defend against soft errors.
In view of the above, efficient methods and systems for efficiently floor planning a memory are desired.